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CS5381
120 dB, 192 kHz, Multi-Bit Audio A/D Converter
Features
! Advanced Multi-bit Delta-Sigma Architecture ! 24-bit Conversion ! 120 dB Dynamic Range ! -110 dB THD+N ! Supports All Audio Sample Rates Including
General Description
The CS5381 is a complete analog-to-digital converter for digital audio systems. It performs sampling, analogto-digital conversion, and anti-alias filtering - generating 24-bit values for both left and right inputs in serial form at sample rates up to 216 kHz per channel. The CS5381 uses a 5th-order, multi-bit delta-sigma modulator followed by digital filtering and decimation, which removes the need for an external anti-alias filter. The ADC uses a differential architecture which provides excellent noise rejection. The CS5381 is available in 24-pin TSSOP and SOIC packages for Commercial grade (-10 to +70 C). The CDB5381 Customer Demonstration board is also available for device evaluation and implementation suggestions. Please refer to the "Ordering Information" on page 22. The CS5381 is ideal for audio systems requiring wide dynamic range, negligible distortion, and low noise such as A/V receivers, DVD-R, CD-R, digital mixing consoles, and effects processors.
192 kHz
! 260 mW Power Consumption ! High-Pass Filter or DC Offset Calibration ! Supports Logic Levels between 5 and 2.5 V ! Differential Analog Architecture ! Low-Latency Digital Filtering ! Overflow Detection ! Pin-Compatible with the CS5361
Analog Supply 5V
Digital Supply 3.3 V to 5 V
Interface Supply 2.5 V to 5 V
Internal Voltage Reference Level Translator
Reset Mode Configuration HPF OVFL PCM Serial Audio Output
Differential Inputs
Switch-Cap ADC
Digital Filters
Differential Inputs
Switch-Cap ADC
Digital Filters
http://www.cirrus.com
Copyright (c) Cirrus Logic, Inc. 2005 (All Rights Reserved)
JULY '05 DS563F2
CS5381
TABLE OF CONTENTS
1. PIN DESCRIPTIONS ............................................................................................................................... 4 2. CHARACTERISTICS AND SPECIFICATIONS....................................................................................... 5 SPECIFIED OPERATING CONDITIONS .................................................................................................... 5 ABSOLUTE MAXIMUM RATINGS............................................................................................................... 5 ANALOG CHARACTERISTICS (CS5381-KSZ/-KZZ).................................................................................. 6 DIGITAL FILTER CHARACTERISTICS....................................................................................................... 7 SWITCHING CHARACTERISTICS - SERIAL AUDIO PORT .................................................................... 10 DC ELECTRICAL CHARACTERISTICS.................................................................................................... 13 DIGITAL CHARACTERISTICS .................................................................................................................. 13 THERMAL CHARACTERISTICS .............................................................................................................. 13 TYPICAL CONNECTION DIAGRAM ......................................................................................................... 14 3. APPLICATIONS .................................................................................................................................... 15 3.1 Operational Mode/Sample Rate Range Select.............................................................................. 15 3.2 System Clocking ............................................................................................................................ 15 3.2.1 Master Mode ........................................................................................................................ 15 3.2.2 Slave Mode .......................................................................................................................... 16 3.3 Power-Up Sequence ..................................................................................................................... 16 3.4 Analog Connections ...................................................................................................................... 16 3.5 High-Pass Filter and DC Offset Calibration .................................................................................. 17 3.6 Overflow Detection ........................................................................................................................ 18 3.6.1 OVFL Configuration ............................................................................................................. 18 3.6.2 OVFL Output Timing ............................................................................................................ 18 3.7 Grounding and Power Supply Decoupling..................................................................................... 18 3.8 Synchronization of Multiple Devices .............................................................................................. 18 3.9 Capacitor Size on the Reference Pin (FILT+)................................................................................ 19 4. PACKAGE DIMENSIONS ..................................................................................................................... 20 5. ORDERING INFORMATION ................................................................................................................. 22 7. REVISION HISTORY ............................................................................................................................. 24
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CS5381
LIST OF FIGURES
Figure 1. Single-Speed Mode Stopband Rejection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 2. Single-Speed Mode Transition Band . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 3. Single-Speed Mode Transition Band (Detail). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 4. Single-Speed Mode Passband Ripple . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 5. Double-Speed Mode Stopband Rejection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 6. Double-Speed Mode Transition Band . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 7. Double-Speed Mode Transition Band (Detail) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 8. Double-Speed Mode Passband Ripple . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 9. Quad-Speed Mode Stopband Rejection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 10. Quad-Speed Mode Transition Band . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 11. Quad-Speed Mode Transition Band (Detail) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 12. Quad-Speed Mode Passband Ripple . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 13. Master Mode, Left-Justified SAI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 14. Slave Mode, Left-Justified SAI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 15. Master Mode, IS SAI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 16. Slave Mode, IS SAI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 17. OVFL Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 18. Left-Justified Serial Audio Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 19. IS Serial Audio Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 20. OVFL Output Timing, IS Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 21. OVFL Output Timing, Left-Justified Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 22. Typical Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 23. CS5381 Master Mode Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 24. Recommended Analog Input Buffer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 25. CS5381 THD + N versus Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
LIST OF TABLES
Table 1. CS5381 Mode Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 2. CS5381 Common Master Clock Frequencies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 3. CS5381 Slave Mode Clock Ratios . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
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CS5381 1. PIN DESCRIPTIONS
RST M/S LRCK SCLK MCLK VD GND VL SDOUT MDIV HPF IS/LJ 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 FILT+ REFGND VQ AINR+ AINRVA GND AINLAINL+ OVFL M1 M0
Pin Name
RST M/S LRCK SCLK MCLK VD GND VL SDOUT MDIV HPF IS/LJ M0 M1 OVFL AINL+ AINLVA AINRAINR+ VQ REF_GND FILT+
# 1 2 3 4 5 6 7,18 8 9 10 11 12
Pin Description
Reset (Input) - The device enters a low power mode when low. Master/Slave Mode (Input) - Selects operation as either clock master or slave. Left Right Clock (Input/Output) - Determines which channel, Left or Right, is currently active on the serial audio data line. Serial Clock (Input/Output) - Serial clock for the serial audio interface. Master Clock (Input) - Clock source for the delta-sigma modulator and digital filters. Digital Power (Input) - Positive power supply for the digital section. Ground (Input) - Ground reference. Must be connected to analog ground. Logic Power (Input) - Positive power for the digital input/output. Serial Audio Data Output (Output) - Output for two's complement serial audio data. MCLK Divider (Input) - Enables a master clock divide by two function. High-Pass Filter Enable (Input) - Enables the Digital High-Pass Filter. Serial Audio Interface Format Select (Input) -Selects either the left-justified or IS format for the SAI.
13,14 Mode Selection (Input) - Determines the operational mode of the device. 15 16, 17 19 20, 21 22 23 24
Overflow (Output, open drain) - Detects an overflow condition on both left and right channels. Differential Left Channel Analog Input (Input) - Signals are presented differentially to the delta-sigma modulators via the AINL+/- pins. Analog Power (Input) - Positive power supply for the analog section. Differential Right Channel Analog Input (Input) -Signals are presented differentially to the deltasigma modulators via the AINR+/- pins. Quiescent Voltage (Output) - Filter connection for the internal quiescent reference voltage. Reference Ground (Input) - Ground reference for the internal sampling circuits. Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling circuits.
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CS5381 2. CHARACTERISTICS AND SPECIFICATIONS
All Min/Max characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical performance characteristics and specifications are derived from measurements taken at VA = 5.0 V, VD = VL = 3.3 V, and TA = 25C.
SPECIFIED OPERATING CONDITIONS
(GND = 0 V; all voltages with respect to 0 V.) Parameters
DC Power Supply DC Power Supplies: Positive Analog Positive Digital Positive Logic
Symbol VA VD VL TA
Min 4.75 3.1 2.37 -10
Typ 5.0 -
Max 5.25 5.25 5.25 +70
Units V V V C
Ambient Operating Temperature (Power Applied)
ABSOLUTE MAXIMUM RATINGS
(GND = 0 V, All voltages with respect to ground.) (Note 1) Parameter
DC Power Supplies: Analog Logic Digital (Note 2) (Note 3) (Note 3)
Symbol VA VL VD Iin VIN VIND TA Tstg
Min -0.3 -0.3 -0.3 -10 GND-0.7 -0.7 -50 -65
Typ -
Max +6.0 +6.0 +6.0 +10 VA+0.7 VL+0.7 +95 +150
Units V V V mA V V C C
Input Current Analog Input Voltage Digital Input Voltage Ambient Operating Temperature (Power Applied) Storage Temperature
Notes: 1. Operation beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. 2. Any pin except supplies. Transient currents of up to 100 mA on the analog input pins will not cause SRC latch-up. 3. The maximum over/under voltage is limited by the input current.
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CS5381 ANALOG CHARACTERISTICS (CS5381-KSZ/-KZZ)
Test conditions (unless otherwise specified): Input test signal is a 1 kHz sine wave; measurement bandwidth is 10 Hz to 20 kHz. Parameter Single-Speed Mode
Dynamic Range Total Harmonic Distortion + Noise
Symbol Fs = 48 kHz
A-weighted unweighted (Note 4) -1 dB -20 dB -60 dB
Min 114 111 -
Typ 120 117 -110 -97 -57
Max -104 -
Unit dB dB dB dB dB
THD+N
Double-Speed Mode
Dynamic Range
Fs = 96 kHz
A-weighted unweighted 40 kHz bandwidth unweighted (Note 4) -1 dB -20 dB -60 dB -1 dB
114 111 114 111 -5 1.07*VA -
120 117 114 -110 -97 -57 -107 120 117 114 -110 -97 -57 -107 110 0.1 -
-104 -104 5 1.18*VA -
dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB % ppm/C LSB LSB Vpp k dB
Total Harmonic Distortion + Noise
THD+N
40 kHz bandwidth
Quad-Speed Mode
Dynamic Range
Fs = 192 kHz
A-weighted unweighted 40 kHz bandwidth unweighted (Note 4) -1 dB -20 dB -60 dB -1 dB
Total Harmonic Distortion + Noise
THD+N
40 kHz bandwidth
Dynamic Performance for All Modes
Interchannel Isolation
DC Accuracy
Interchannel Gain Mismatch Gain Error Gain Drift Offset Error HPF enabled HPF disabled
100
0 100 1.13*VA 2.5 100
Analog Input Characteristics
Full-scale Input Voltage Input Impedance (Differential) Common Mode Rejection Ratio (Note 5)
CMRR
4. Referred to the typical full-scale input voltage. 5. Measured between AIN+ and AIN-.
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CS5381 DIGITAL FILTER CHARACTERISTICS
Parameter Single-Speed Mode (2 kHz to 54 kHz sample rates)
Passband Passband Ripple Stopband Stopband Attenuation Total Group Delay (Fs = Output Sample Rate) (Note 6) (-0.1 dB) (Note 6)
Symbol
Min 0 -0.1 0.58 -95
Typ 12/Fs 9/Fs 5/Fs 1 20 10 105/Fs
Max 0.47 0.035 0.45 0.035 0.24 0.035 0
Unit Fs dB Fs dB s Fs dB Fs dB s Fs dB Fs dB s Hz Hz Deg dB s
tgd
(Note 6) (Note 6)
0 -0.1 0.68 -92
Double-Speed Mode (50 kHz to 108 kHz sample rates)
Passband Passband Ripple Stopband Stopband Attenuation Total Group Delay (Fs = Output Sample Rate) (-0.1 dB)
tgd
(Note 6) (Note 6)
0 -0.1 0.78 -97
Quad-Speed Mode (100 kHz to 216 kHz sample rates)
Passband Passband Ripple Stopband Stopband Attenuation Total Group Delay (Fs = Output Sample Rate) (-0.1 dB)
tgd
-
High-Pass Filter Characteristics
Frequency Response Phase Deviation Passband Ripple Filter Setting Time -3.0 dB -0.13 dB @ 20 Hz (Note 7) (Note 7)
-
6. The filter frequency response scales precisely with Fs. 7. Response shown is for Fs equal to 48 kHz. Filter characteristics scale with Fs.
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CS5381
0 -10 -20 -30 -40 -50 Amplitude (dB) -60 -70 -80 -90 -100 -110 -120 -130 -140 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 Frequency (normalized to Fs)
0 -10 -20 -30 -40 -50 Amplitude (dB) -60 -70 -80 -90 -100 -110 -120 -130 -140 0.40
0.42
0.44
0.46
0.48
0.50
0.52
0.54
0.56
0.58
0.60
Frequency (normalized to Fs)
Figure 1. Single-Speed Mode Stopband Rejection
Figure 2. Single-Speed Mode Transition Band
0
0.10
-1
0.08
-2
0.05
-3
0.03 Amplitude (dB)
Amplitude (dB)
-4
-5
0.00
-6
-0.03
-7
-0.05
-8
-0.08
-9
-10 0.45
0.46
0.47
0.48
0.49
0.50
0.51
0.52
0.53
0.54
0.55
-0.10 0.00
0.05
0.10
0.15
0.20
0.25
0.30
0.35
0.40
0.45
0.50
Frequency (normalized to Fs)
Frequency (normalized to Fs)
Figure 3. Single-Speed Mode Transition Band (Detail)
Figure 4. Single-Speed Mode Passband Ripple
0 0 -10 -10 -20 -20 -30 -30 -40 -40 -50 Amplitude (dB) -50 Amplitude (dB) -60 -70 -80 -90 -100 -100 -110 -110 -120 -120 -130 -130 -140 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 Frequency (normalized to Fs) -140 0.40 0.43 0.45 0.48 0.50 0.53 0.55 0.58 0.60 0.63 0.65 0.68 0.70 -60 -70 -80 -90
Frequency (normalized to Fs)
Figure 5. Double-Speed Mode Stopband Rejection
Figure 6. Double-Speed Mode Transition Band
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CS5381
0 0.10
-1 0.08 -2 0.05 -3 0.03 Amplitude (dB) 0.43 0.45 0.48 Frequency (normalized to Fs) 0.50 0.53 0.55
Amplitude (dB)
-4
-5
0.00
-6
-0.03 -7 -0.05 -8 -0.08
-9
-10 0.40
-0.10 0.00
0.05
0.10
0.15
0.20
0.25
0.30
0.35
0.40
0.45
0.50
Frequency (normalized to Fs)
Figure 7. Double-Speed Mode Transition Band (Detail)
Figure 8. Double-Speed Mode Passband Ripple
0 -10 -20 -30
0 -10 -20 -30 -40
-40 Amplitude (dB) -50 -60 -70 -80 -90 -100 -110 -120 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 Frequency (normalized to Fs) Amplitude (dB) -50 -60 -70 -80 -90 -100 -110 -120 -130 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 0.8 Frequency (normalized to Fs)
Figure 9. Quad-Speed Mode Stopband Rejection
Figure 10. Quad-Speed Mode Transition Band
0
0.10
-1
0.08
-2
0.06
-3
0.04
Amplitude (dB)
Amplitude (dB)
-4
0.02
-5
0.00
-6
-0.02
-7
-0.04
-8
-0.06
-9
-0.08
-10 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6 Frequency (normalized to Fs)
-0.10 0.00
0.05
0.10
0.15
0.20
0.25
Frequency (normalized to Fs)
Figure 11. Quad-Speed Mode Transition Band (Detail)
Figure 12. Quad-Speed Mode Passband Ripple
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CS5381 SWITCHING CHARACTERISTICS - SERIAL AUDIO PORT
(Logic "0" = GND = 0 V; Logic "1" = VL, CL = 20 pF) Parameter
Output Sample Rate Single-Speed Mode Double-Speed Mode Quad-Speed Mode
Symbol Fs Fs Fs tsetup thold
Min 2 50 100 16/fsclk 1/fsclk -
Typ 740 680 50
Max 54 108 216 1953 60 20 32 -
Unit kHz kHz kHz s s ms ms ns % ns ns %
OVFL to LRCK Edge Setup Time OVFL to LRCK Edge Hold Time
OVFL time-out on overrange condition
Fs = 44.1, 88.2, 176.4 kHz Fs = 48, 96, 192 kHz
MCLK Specifications
MCLK Period MCLK Duty Cycle
tclkw
36 40
Master Mode
SCLK falling to LRCK transition SCLK falling to SDOUT valid SCLK Duty Cycle
tmslr tsdo
-20 -
Slave Mode Single-Speed
Output Sample Rate LRCK Duty Cycle SCLK Period SCLK Duty Cycle SDOUT valid before SCLK rising SDOUT valid after SCLK rising SCLK falling to LRCK transition
Fs tsclkw tstp thld tslrd Fs tsclkw tstp thld tslrd Fs tsclkw tstp thld tslrd
2 40 145 45 10 5 -20 50 40 145 45 10 5 -20 100 40 72 45 10 5 -8
50 50 50 50 50 50 -
54 60 55 20 108 60 55 20 216 60 55 8
kHz % ns % ns ns ns kHz % ns % ns ns ns kHz % ns % ns ns ns DS563F2
Double-Speed
Output Sample Rate LRCK Duty Cycle SCLK Period SCLK Duty Cycle SDOUT valid before SCLK rising SDOUT valid after SCLK rising SCLK falling to LRCK transition
Quad-Speed
Output Sample Rate LRCK Duty Cycle SCLK Period SCLK Duty Cycle SDOUT valid before SCLK rising SDOUT valid after SCLK rising SCLK falling to LRCK transition
10
CS5381
LRCK output
tmslr
LRCK input
t slrd
SCLK output
t sdo
SCLK input
t sclkh t stp t hld
t sclkl
SDOUT
MSB
MSB-1
MSB-2
MSB-3
SDOUT
MSB
MSB-1
Figure 13. Master Mode, Left-Justified SAI
Figure 14. Slave Mode, Left-Justified SAI
LRCK output
tmslr
LRCK input
t slrd
SCLK output
t sdo
SCLK input
t sclkh
t sclkl t stp t hld
SDOUT
MSB
MSB-1
MSB-2 MSB-3
SDOUT
MSB
Figure 15. Master Mode, IS SAI
Figure 16. Slave Mode, IS SAI
LRCK t setup OVFL t hold
Figure 17. OVFL Output Timing
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CS5381
LRCK
Left Channel
Right Channel
SCLK
SDATA
23
22
9876543210
23
22
9876543210
23
22
Figure 18. Left-Justified Serial Audio Interface
LRCK
Left Channel
Right Channel
SCLK
SDATA
23
22
9876543210
23
22
9876543210
23
22
Figure 19. IS Serial Audio Interface
LRCK
Left Channel Frame
Right Channel Frame
SCLK
OVFL
OVFL on Left Chan
OVFL on Right Chan
Figure 20. OVFL Output Timing, IS Format
LRCK
L e ft C h a n n e l F r a m e
R ig h t C h a n n e l F r a m e
SC LK
OVFL
O V F L o n R ig h t C h a n
O V F L o n L e ft C han
Figure 21. OVFL Output Timing, Left-Justified Format
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CS5381 DC ELECTRICAL CHARACTERISTICS
(GND = 0 V, all voltages with respect to ground. MCLK=12.288 MHz; Master Mode) Parameter
Power Supply Current (Normal Operation) Power Supply Current (Power-Down Mode) (Note 8) Power Consumption (Normal Operation) VA = 5 V VL,VD = 5 V VL,VD = 3.3 V VA = 5 V VL,VD = 5 V VA, VL, VD = 5 V VA = 5 V; VL, VD = 3.3 V (Power-Down Mode) (Note 9)
Symbol IA ID ID IA ID PSRR
Min -
Typ 36 36 24 100 100 360 260 1 65 2.5 25 0.01 5 4.5 0.01
Max 43 46 28 445 307 -
Unit mA mA mA uA uA mW mW mW dB V k mA V k mA
Power Supply Rejection Ratio (1 kHz) VQ Nominal Voltage
Output Impedance Maximum allowable DC current source/sink Filt+ Nominal Voltage Output Impedance Maximum allowable DC current source/sink
8. Power-Down Mode is defined as RST = Low with all clocks and data lines held static. 9. Valid with the recommended capacitor values on FILT+ and VQ as shown in the Typical Connection Diagram.
DIGITAL CHARACTERISTICS
Parameter
High-Level Input Voltage Low-Level Input Voltage High-Level Output Voltage at Io = 100 A Low-Level Output Voltage at Io = 100 A OVFL Current Sink Input Leakage Current (% of VL) (% of VL) (% of VL) (% of VL)
Symbol VIH VIL VOH VOL Iovfl Iin
Min 70% 70% -10
Typ -
Max 30% 15% 4.0 10
Units V V V V mA A
THERMAL CHARACTERISTICS
Parameter
Allowable Junction Temperature Junction to Ambient Thermal Impedance (Multi-layer PCB) TSSOP (Multi-layer PCB) SOIC (Single-layer PCB) TSSOP (Single-layer PCB) SOIC
Symbol
Min -
Typ 70 60 105 80
Max 135 -
Unit C C/W C/W C/W C/W
JA-TM JA-SM JA-TS JA-SS
-
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CS5381 TYPICAL CONNECTION DIAGRAM
+5 V to 3.3 V
+ 1 F
0.01F
*
0.01 F 0.01 F
+
1 F
+5Vto 2.5 V
+5V
+
1 F
0.01 F
5.1
VA FILT+ **47 F + 0.01 F REFGND + 1 F 0.01 F VQ
VD
VL VL 10 k OVFL RST 2 I S/LJ M/S HPF M0 M1 MDIV
Analog Input Buffer (Figure 24)
AINL+
CS5381 A/D CONVERTER
Power Down and Mode Settings
AINLSDOUT Audio Data Processor
Analog Input Buffer (Figure 24)
AINR+
LRCK SCLK MCLK Timing Logic and Clock
AINR* Resistor may only be used if VD is derived from VA. If used, do not drive any other logic from VD.
GND
GND
** Capacitor value affects low frequency distortion. See Section 3.9.
Figure 22. Typical Connection Diagram
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CS5381 3. APPLICATIONS
3.1 Operational Mode/Sample Rate Range Select
The output sample rate, Fs, can be adjusted from 2 kHz to 216 kHz. The CS5381 must be set to the proper speed mode via the mode pins, M1 and M0. Refer to Table 1.
M1 (Pin 14) 0 0 1 1
M0 (Pin 13) 0 1 0 1
MODE
Single-Speed Mode Double-Speed Mode Quad-Speed Mode Reserved Table 1. CS5381 Mode Control
Output Sample Rate (Fs)
2 kHz - 54 kHz 50 kHz - 108 kHz 100 kHz - 216 kHz
3.2
System Clocking
The device supports operation in either Master Mode, where the left/right and serial clocks are synchronously generated on-chip, or Slave Mode, which requires external generation of the left/right and serial clocks. The device also includes a master clock divider in Master Mode where the master clock will be internally divided prior to any other internal circuitry when MDIV is enabled, set to logic 1. In Slave Mode, the MDIV pin needs to be disabled, set to logic 0.
3.2.1
Master Mode
In Master mode, LRCK and SCLK operate as outputs. The left/right and serial clocks are internally derived from the master clock with the left/right clock equal to Fs and the serial clock equal to 64x Fs, as shown in Figure 23. Refer to Table 2 for common master clock frequencies.
/ 256 / 128 / 64 /1 MCLK /2 1 /4 MDIV /2 /1 0
Single Speed Double Speed Quad Speed
00 01 10
LRCK Output (Equal to Fs)
M1 M0
Single Speed Double Speed Quad Speed
00 01 10
SCLK Output
Figure 23. CS5381 Master Mode Clocking
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CS5381
MDIV = 0 MCLK (MHz)
8.192 11.2896 12.288 8.192 11.2896 12.288 11.2896 12.288 Table 2. CS5381 Common Master Clock Frequencies
SAMPLE RATE (kHz)
32 44.1 48 64 88.2 96 176.4 192
MDIV = 1 MCLK (MHz)
16.384 22.5792 24.576 16.384 22.5792 24.576 22.5792 24.576
3.2.2
Slave Mode
LRCK and SCLK operate as inputs in Slave mode. It is recommended that the left/right clock be synchronously derived from the master clock and must be equal to Fs. It is also recommended that the serial clock be synchronously derived from the master clock and be equal to 64x Fs to maximize system performance. Refer to Table 3 for required clock ratios. Single-Speed Mode Double-Speed Mode Quad-Speed Mode Fs = 2 kHz to 54 kHz Fs = 50 kHz to 108 kHz Fs = 100 kHz to 216 kHz
MCLK/LRCK Ratio SCLK/LRCK Ratio
256x, 512x 64x, 128x
128x, 256x 64x
64x*, 128x 64x
* Only available in Master mode.
Table 3. CS5381 Slave Mode Clock Ratios
3.3
Power-Up Sequence
Reliable power-up can be accomplished by keeping the device in reset until the power supplies, clocks and configuration pins are stable. It is also recommended that reset be enabled if the analog or digital supplies drop below the minimum specified operating voltages to prevent power glitch related issues. The internal reference voltage must be stable for the device to produce valid data. Therefore, there is a delay between the release of reset and the generation of valid output, due to the finite output impedance of FILT+ and the presence of the external capacitance. This duration of this delay is less than 2500 LRCK cycles.
3.4
Analog Connections
The analog modulator samples the input at 6.144 MHz. The digital filter will reject signals within the stopband of the filter. However, there is no rejection for input signals which are (n x 6.144 MHz) the digital passband frequency, where n=0,1,2,... Refer to Figure 24, which shows the suggested filter that will attenuate any noise energy at 6.144 MHz in addition to providing the optimum source impedance for the modulators. The use of capacitors which have a large voltage coefficient (such as general purpose ceramics) must be avoided since these can degrade signal linearity. C0G capacitors are recommended for this application.
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634
470 pF COG 10 uF AIN+ 100k 10 k COG VQ 10 k 10 uF AIN100k + 470 pF COG 634 91 ADC AIN2700 pF + 91 ADC AIN+
Figure 24. Recommended Analog Input Buffer
3.5
High-Pass Filter and DC Offset Calibration
The operational amplifiers in the input circuitry driving the CS5381 may generate a small DC offset into the A/D converter. The CS5381 includes a high-pass filter after the decimator to remove any DC offset which could result in recording a DC level, possibly yielding "clicks" when switching between devices in a multichannel system. The high-pass filter continuously subtracts a measure of the DC offset from the output of the decimation filter. If the HPF pin is taken high during normal operation, the current value of the DC offset register is frozen and this DC offset will continue to be subtracted from the conversion result. This feature makes it possible to perform a system DC offset calibration by: 1. Running the CS5381 with the high-pass filter enabled until the filter settles. See the Digital Filter Characteristics for filter settling time. 2. Disabling the high-pass filter and freezing the stored DC offset. A system calibration performed in this way will eliminate offsets anywhere in the signal path between the calibration point and the CS5381.
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3.6 Overflow Detection
The CS5381 includes overflow detection on both the left and right channels. This time multiplexed information is presented as open drain, active low on pin 15, OVFL. The OVFL_L and OVFL_R data will go to a logical low as soon as an overrange condition in the opposite channel is detected. The data will remain low as specified in the "Switching Characteristics - Serial Audio Port" section on page 10. This ensures sufficient time to detect an overrange condition regardless of the speed mode. After the timeout, the OVFL_L and OVFL_R data will return to a logical high if there has not been any other overrange condition detected. Please note that an overrange condition on either channel will restart the timeout period for both channels.
3.6.1
OVFL Configuration
If the system does not require overflow detection, the user may leave the OVFL pin disconnected. When using the overflow detection capability of the CS5381, a 10 k pull-up resistor must be inserted between the OVFL pin and VL because the OVFL output is open drain, active low. This means that the OVFL pin is high impedance for the case of no overflow condition, but the pull-up resistor will pull the node to VL. When an overflow condition occurs, the OVFL pin can drive the node to GND thus indicating the presence of the overflow condition. In effect, the user can use the OVFL pin to illuminate an LED, or mute the channel with an external circuit or a DSP. Furthermore, because the OVFL output is open-drain, the OVFL pins of multiple CS5381 devices can be tied together such that an overflow condition on a single device will drive the line low. When connecting OVFL pins of multiple devices, only a single 10k pull-up resistor is necessary.
3.6.2
OVFL Output Timing
In left-justified format, the OVFL pin is updated one SCLK period after an LRCK transition. In IS format, the OVFL pin is updated two SCLK periods after an LRCK transition. Refer to Figures 20 and 21. In both cases, the OVFL data can be easily demultiplexed by using the LRCK to latch the data. In left-justified format, the rising edge of LRCK would latch the right channel overflow status, and the falling edge of LRCK would latch the left channel overflow status. In IS format, the falling edge of LRCK would latch the right channel overflow status and the rising edge of LRCK would latch the left channel overflow status.
3.7
Grounding and Power Supply Decoupling
As with any high resolution converter, the CS5381 requires careful attention to power supply and grounding arrangements if its potential performance is to be realized. Figure 22 shows the recommended power arrangements, with VA and VL connected to clean supplies. VD, which powers the digital filter, may be run from the system logic supply or may be powered from the analog supply via a resistor. In this case, no additional devices should be powered from VD. Decoupling capacitors should be as near to the ADC as possible, with the low value ceramic capacitor being the nearest. All signals, especially clocks, should be kept away from the FILT+ and VQ pins in order to avoid unwanted coupling into the modulators. The FILT+ and VQ decoupling capacitors, particularly the 0.01 F, must be positioned to minimize the electrical path from FILT+ and REFGND. The CDB5381 evaluation board demonstrates the optimum layout and power supply arrangements. To minimize digital noise, connect the ADC digital outputs only to CMOS inputs.
3.8
Synchronization of Multiple Devices
In systems where multiple ADCs are required, care must be taken to achieve simultaneous sampling. To ensure synchronous sampling, the MCLK and LRCK must be the same for all of the CS5381's in the system. If only one master clock source is needed, one solution is to place one CS5381 in Master mode, and slave all of the other CS5381's to the one master. If multiple master clock sources are needed, a possible solution would be to supply all clocks from the same external source and time the CS5381 reset with the falling edge of MCLK. This will ensure that all converters begin sampling on the same clock edge.
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3.9 Capacitor Size on the Reference Pin (FILT+)
The CS5381 requires an external capacitance on the internal reference voltage pin, FILT+. The size of this decoupling capacitor will affect the low frequency distortion performance as shown in Figure 25, with larger capacitor values used to optimize low frequency distortion performance. The THD+N curves in Figure 25 were measured with VA=VD=VL=5 V in Single-Speed Master Mode with a full-scale sinewave input.
1 uF
10 uF 22 uF
47 uF 100 uF 220 uF
Figure 25. CS5381 THD + N versus Frequency
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CS5381 4. PACKAGE DIMENSIONS 24L SOIC (300 MIL BODY) PACKAGE DRAWING
E
H
1 b c D SEATING PLANE e A1 L A
INCHES DIM A A1 B C D E e H L MIN 0.093 0.004 0.013 0.009 0.598 0.291 0.040 0.394 0.016 0 MAX 0.104 0.012 0.020 0.013 0.614 0.299 0.060 0.419 0.050 8
MILLIMETERS MIN MAX 2.35 0.10 0.33 0.23 15.20 7.40 1.02 10.00 0.40 0 2.65 0.30 0.51 0.32 15.60 7.60 1.52 10.65 1.27 8
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CS5381 24L TSSOP (4.4 mm BODY) PACKAGE DRAWING
N
D
E11 A2 A1
L
E
A
e b2 SIDE VIEW
123
END VIEW
SEATING PLANE
TOP VIEW
DIM A A1 A2 b D E E1 e L
MIN -0.002 0.03346 0.00748 0.303 0.248 0.169 -0.020 0
INCHES NOM -0.004 0.0354 0.0096 0.307 0.2519 0.1732 0.026 BSC 0.024 4
MAX 0.043 0.006 0.037 0.012 0.311 0.256 0.177 -0.028 8
MIN -0.05 0.85 0.19 7.70 6.30 4.30 -0.50 0
MILLIMETERS NOM --0.90 0.245 7.80 6.40 4.40 0.65 BSC 0.60 4
NOTE MAX 1.10 0.15 0.95 0.30 7.90 6.50 4.50 -0.70 8
2,3 1 1
JEDEC #: MO-153 Controlling Dimension is Millimeters. Notes: 1. "D" and "E1" are reference datums and do not included mold flash or protrusions, but do include mold mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per side. 2. Dimension "b" does not include dambar protrusion/intrusion. Allowable dambar protrusion shall be 0.13 mm total in excess of "b" dimension at maximum material condition. Dambar intrusion shall not reduce dimension "b" by more than 0.07 mm at least material condition. 3. These dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips.
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CS5381 5. ORDERING INFORMATION
Product
CS5381 CS5381
Description
Package
Pb-Free
Yes Yes -
Grade
Temp Range
Container
Bulk Bulk -
Order #
CS5381-KZZ CS5381-KSZ CDB5381
120 dB, 192 kHz, Multi-Bit 24-TSSOP Audio A/D Converter 120 dB, 192 kHz, Multi-Bit Audio A/D Converter 24-SOIC -
Commercial -10 to +70 C Commercial -10 to +70 C -
Tape & Reel CS5381-KZZR Tape & Reel CS5381-KSZR
CDB5381 CS5381 Evaluation Board
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6 PARAMETER DEFINITIONS
Dynamic Range The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth. Dynamic Range is a signal-to-noise ratio measurement over the specified bandwidth made with a -60 dBFS signal. 60 dB is added to resulting measurement to refer the measurement to full-scale. This technique ensures that the distortion components are below the noise level and do not affect the measurement. This measurement technique has been accepted by the Audio Engineering Society, AES17-1991, and the Electronic Industries Association of Japan, EIAJ CP-307. Expressed in decibels. Total Harmonic Distortion + Noise The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth (typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels. Measured at -1 and -20 dBFS as suggested in AES17-1991 Annex A. Frequency Response A measure of the amplitude response variation from 10 Hz to 20 kHz relative to the amplitude response at 1 kHz. Units in decibels. Interchannel Isolation A measure of crosstalk between the left and right channels. Measured for each channel at the converter's output with no signal to the input under test and a full-scale signal applied to the other channel. Units in decibels. Interchannel Gain Mismatch The gain difference between left and right channels. Units in decibels. Gain Error The deviation from the nominal full-scale analog input for a full-scale digital output. Gain Drift The change in gain value with temperature. Units in ppm/C. Offset Error The deviation of the mid-scale transition (111...111 to 000...000) from the ideal. Units in mV.
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CS5381 7. REVISION HISTORY
Release A1 A2 Date December 2002 Initial Release October 2003 Changes
Changed front page description of digital filter Improved distortion specification from -105 dB to -110 dB Modified serial port timing specifications for slave mode operation Added pull-down resistors to recommended input buffer Changed full-scale voltage specification to reflect VA supply voltage Added Applications section about capacitor value on FILT+ pin Changed input impedance specification from 37 to 2.5 k Changed impedance specification on FILT+ from 35 to 4.5 k Add Lead free part number Replaced diagrams showing OVFL functionality (see Figures 20 and 21) Replaced Figures 13, 15, 18 and 19 to demonstrate pre-emption of the MSB. Increased maximum digital current (ID) specification at 5 V from 43 mA to 46 mA. . Updated Ordering Information.
A3 A4 F1 F2
May 2004 August 2004 July 2005 July 2005
Contacting Cirrus Logic Support
For all product questions and inquiries contact a Cirrus Logic Sales Representative. To find the one nearest to you go to www.cirrus.com
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